Verification techniques for system-level design (Record no. 120986)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01581nam a22003974a 4500 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| 100 1# - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Fujita, Masahiro, |
| 245 10 - TITLE STATEMENT | |
| Title | Verification techniques for system-level design |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Amsterdam ; |
| -- | Boston : |
| Name of publisher | Morgan Kaufmann Publishers, |
| Year of publication | c2008. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | viii, 240 p. : |
| Other physical details | ill. |
| 490 1# - SERIES STATEMENT | |
| Series statement | The Morgan Kaufmann series in systems on silicon |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Systems on a chip |
| Topical Term | Integrated circuits |
| Topical Term | Formal methods (Computer science) |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Ghosh, Indradeep, |
| Personal name | Prasad, Mukul. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://site.ebrary.com/lib/rucke/Doc?id=10203637 |
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