header

Embedded SoPC design with NIOS II processor and Verilog examples (Record no. 52812)

MARC details
000 -LEADER
fixed length control field 02137nam a2200349 a 4500
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 006.2/2
100 1# - MAIN ENTRY--AUTHOR NAME
Personal name Chu, Pong P.,
245 10 - TITLE STATEMENT
Title Embedded SoPC design with NIOS II processor and Verilog examples
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication Hoboken, N.J. :
Name of publisher Wiley,
Year of publication c2012.
300 ## - PHYSICAL DESCRIPTION
Number of Pages xxxiii, 747 p. :
Other physical details ill.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies.
520 ## - SUMMARY, ETC.
Summary, etc "This book explores the unique hardware programmability of FPGA (field-programmable gate array)-based embedded systems, using a learning-by-doing approach to introduce the concepts and techniques for embedded SoPC (system on a programmable chip) systems with Verilog. The book contains a large number of practical examples to illustrate and reinforce the hardware and software design concepts and techniques, as well as a complete code listing and experiment problems. The book is designed for upper-level undergraduate and entry-level graduate students in computer engineering, as well as practicing engineers"--
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Embedded computer systems.
Topical Term Field programmable gate arrays.
Topical Term Verilog (Computer hardware description language)
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://site.ebrary.com/lib/rucke/Doc?id=10630577
520 ## - SUMMARY, ETC.
-- Provided by publisher.

No items available.

© 2026 Rongo University
Contact us: librarian | system librarian | Rongo university