FSM-based digital design using Verilog HDL (Record no. 67478)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01436nam a2200373 a 4500 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004/.33 |
| 100 1# - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Minns, Peter D. |
| 245 10 - TITLE STATEMENT | |
| Title | FSM-based digital design using Verilog HDL |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Chichester, England ; |
| -- | Hoboken, NJ : |
| Name of publisher | J. Wiley & Sons, |
| Year of publication | c2008. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xiii, 391 p. : |
| Other physical details | ill. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Verilog (Computer hardware description language) |
| Topical Term | Digital electronics. |
| Topical Term | Sequential machine theory. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Elliott, Ian D. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://site.ebrary.com/lib/rucke/Doc?id=10301213 |
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