01351nam a2200325Ia 4500001001200000003000800012006001900020007001500039008004100054010001700095020002300112020002800135040002100163035002000184050002700204100002100231245010900252260004500361300002600406504005100432533015200483650002700635650003900662650009700701650003500798655002900833700002000862710001700882856012600899ebr10053328CaPaEBRm        u        cr cn|||||||||960502r20021996maua    sb    001 0 eng d  z   96021769   z0306475928 (eBook)  z0792397460 (alk. paper)  aCaPaEBRcCaPaEBR  a(OCoLC)7075720414aTK7874.75b.H33 2002eb1 aHachtel, Gary D.10aLogic synthesis and verification algorithmsh[electronic resource] /cby Gary D. Hachtel, Fabio Somenzi.  aBoston :bKluwer Academic,cc2002, 1996.  axxxii, 597 p. :bill.  aIncludes bibliographical references and index.  aElectronic reproduction.bPalo Alto, Calif. :cebrary,d2009.nAvailable via World Wide Web.nAccess may be limited to ebrary affiliated libraries. 0aComputer-aided design. 0aIntegrated circuitsxVerification. 0aIntegrated circuitsxVery large scale integrationxDesign and constructionxData processing. 0aLogic designxData processing. 7aElectronic books.2local1 aSomenzi, Fabio.2 aebrary, Inc.40uhttp://site.ebrary.com/lib/rucke/Doc?id=10053328zAn electronic book accessible through the World Wide Web; click to view