01234nam a2200313Ia 4500001001200000003000800012006001900020007001500039008004100054010001700095015001500112020002800127040002100155035002100176050002700197245012400224260005000348300001900398504004100417533015200458650004800610650002900658650001900687655002900706700002500735710001700760856012600777999001700903ebr10078634CaPaEBRm        u        cr cn|||||||||030814s2003    maua    sb    000 0 eng d  z  2003061861  aGBA3-V6241  z1402075944 (alk. paper)  aCaPaEBRcCaPaEBR  a(OCoLC)22811420714aTK7895.E42bS97 2003eb00aSystem level design model with re-use of system IPh[electronic resource] /cedited by Patrizia Cavalloro ... [et al.].  aBoston :bKluwer Academic Publishers,cc2003.  a211 p. :bill.  aIncludes bibliographical references.  aElectronic reproduction.bPalo Alto, Calif. :cebrary,d2009.nAvailable via World Wide Web.nAccess may be limited to ebrary affiliated libraries. 0aSystems on a chipxDesign and construction. 0aModularity (Engineering) 0aSystem design. 7aElectronic books.2local1 aCavalloro, Patrizia.2 aebrary, Inc.40uhttp://site.ebrary.com/lib/rucke/Doc?id=10078634zAn electronic book accessible through the World Wide Web; click to view  c54598d54598