01375nam a2200313Ia 4500001001200000003000800012006001900020007001500039008004100054020001500095040002100110035002000131050002700151100002700178245017200205250001200377260004100389300002500430504005100455533015200506650007800658650005300736650005700789655002900846700002600875710001700901856012600918999001701044ebr10053381CaPaEBRm        u        cr cn|||||||||040626s2002    nyua   gsb    001 0 eng d  z0306476312  aCaPaEBRcCaPaEBR  a(OCoLC)7075561914aTK7874.75b.B47 2002eb1 aBening, Lionel,d1939-10aPrinciples of verifiable RTL designh[electronic resource] :ba functional coding style supporting verification processes in Verilog /cLionel Bening and Harry Foster.  a2nd ed.  aNew York :bKluwer Academic,cc2002.  axxiv, 281 p. :bill.  aIncludes bibliographical references and index.  aElectronic reproduction.bPalo Alto, Calif. :cebrary,d2009.nAvailable via World Wide Web.nAccess may be limited to ebrary affiliated libraries. 0aIntegrated circuitsxVery large scale integrationxComputer-aided design. 0aVerilog (Computer hardware description language) 0aElectronic digital computersxComputer-aided design. 7aElectronic books.2local1 aFoster, Harry,d1956-2 aebrary, Inc.40uhttp://site.ebrary.com/lib/rucke/Doc?id=10053381zAn electronic book accessible through the World Wide Web; click to view  c65640d65640