01407nam a2200361 a 4500001001200000003000800012006001900020007001500039008004100054010001700095015001900112016001800131020001800149020001500167040002100182035002100203050002600224082001600250100002000266245009900286246006400385260006700449300002500516504005100541533015200592650005300744650002500797650003100822655002900853700002000882710001700902856012600919ebr10301213CaPaEBRm        u        cr cn|||||||||071023s2008    enka    sb    001 0 eng    z  2007043838  aGBA8049942bnb7 z0144882162Uk  z9780470060704  z0470060700  aCaPaEBRcCaPaEBR  a(OCoLC)64778552714aTK7885.7b.M54 2008eb04a004/.332221 aMinns, Peter D.10aFSM-based digital design using Verilog HDLh[electronic resource] /cPeter Minns, Ian Elliott.3 aFinite state machine based digital design using Verilog HDL  aChichester, England ;aHoboken, NJ :bJ. Wiley & Sons,cc2008.  axiii, 391 p. :bill.  aIncludes bibliographical references and index.  aElectronic reproduction.bPalo Alto, Calif. :cebrary,d2013.nAvailable via World Wide Web.nAccess may be limited to ebrary affiliated libraries. 0aVerilog (Computer hardware description language) 0aDigital electronics. 0aSequential machine theory. 7aElectronic books.2local1 aElliott, Ian D.2 aebrary, Inc.40uhttp://site.ebrary.com/lib/rucke/Doc?id=10301213zAn electronic book accessible through the World Wide Web; click to view