000			01234nam a2200313Ia 4500
001			ebr10078634
003			CaPaEBR
006			m u
007			cr cn|||||||||
008			030814s2003 maua sb 000 0 eng d
010			_z 2003061861
015			_aGBA3-V6241
020			_z1402075944 (alk. paper)
040			_aCaPaEBR _cCaPaEBR
035			_a(OCoLC)228114207
050	1	4	_aTK7895.E42 _bS97 2003eb
245	0	0	_aSystem level design model with re-use of system IP _h[electronic resource] / _cedited by Patrizia Cavalloro ... [et al.].
260			_aBoston : _bKluwer Academic Publishers, _cc2003.
300			_a211 p. : _bill.
504			_aIncludes bibliographical references.
533			_aElectronic reproduction. _bPalo Alto, Calif. : _cebrary, _d2009. _nAvailable via World Wide Web. _nAccess may be limited to ebrary affiliated libraries.
650		0	_aSystems on a chip _xDesign and construction.
650		0	_aModularity (Engineering)
650		0	_aSystem design.
655		7	_aElectronic books. _2local
700	1		_aCavalloro, Patrizia.
710	2		_aebrary, Inc.
856	4	0	_uhttp://site.ebrary.com/lib/rucke/Doc?id=10078634 _zAn electronic book accessible through the World Wide Web; click to view
999			_c54598 _d54598