000 01097nam a2200277Ia 4500
001 ebr10053397
003 CaPaEBR
006 m u
007 cr cn|||||||||
008 040626s2002 nyua gs 001 0 eng d
020 _z0306476878
040 _aCaPaEBR
_cCaPaEBR
035 _a(OCoLC)609971605
050 1 4 _aTK7885.7
_b.B47 2002eb
100 1 _aBergeron, Janick.
245 1 0 _aWriting testbenches
_h[electronic resource] :
_bfunctional verification of HDL models /
_cJanick Bergeron.
260 _aNew York :
_bKluwer Academic,
_cc2002.
300 _axxii, 354 p. :
_bill.
500 _aIncludes index.
533 _aElectronic reproduction.
_bPalo Alto, Calif. :
_cebrary,
_d2009.
_nAvailable via World Wide Web.
_nAccess may be limited to ebrary affiliated libraries.
650 0 _aComputer hardware description languages.
650 0 _aIntegrated circuits
_xVerification.
655 7 _aElectronic books.
_2local
710 2 _aebrary, Inc.
856 4 0 _uhttp://site.ebrary.com/lib/rucke/Doc?id=10053397
_zAn electronic book accessible through the World Wide Web; click to view
999 _c65656
_d65656