Logic synthesis and verification algorithms (Record no. 170016)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01382nam a2200337Ia 4500 |
| 100 1# - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Hachtel, Gary D. |
| 245 10 - TITLE STATEMENT | |
| Title | Logic synthesis and verification algorithms |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication | Boston : |
| Name of publisher | Kluwer Academic, |
| Year of publication | c2002, 1996. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xxxii, 597 p. : |
| Other physical details | ill. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | Computer-aided design. |
| Topical Term | Integrated circuits |
| Topical Term | Integrated circuits |
| Topical Term | Logic design |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Somenzi, Fabio. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://site.ebrary.com/lib/rucke/Doc?id=10053328 |
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